Information Technology Reference
In-Depth Information
9.3.2 Asynchronous and isochronous transfer
One of the key capabilities of IEEE-1394 is isochronous data transfer. Both asynchronous
and isochronous are supported, and are useful for different applications. Isochronous trans-
mission transmits data like real-time speech and video, both of which must be delivered
uninterrupted, and at the rate expected, whereas asynchronous transmission is used to
transfer data that is not tied to a specific transfer time. With IEEE-1394, asynchronous is the
conventional transfer method of sending data to an explicit address, and receiving
confirmation when it is received. Isochronous, however, is an unacknowledged guaranteed-
bandwidth transmission method, useful for just-in-time delivery of multimedia-type data.
An isochronous 'talker', requests an amount of bandwidth and a channel number. Once
the bandwidth has been allocated, it can transmit data preceded by a channel ID. The
isochronous
listeners
can then listen for the specified channel ID and accept the data follow-
ing. If the data is not intended for a node, it will not be set to listen on the specific channel
ID. Up to 64 isochronous channels are available, and these must be allocated, along with
their respective bandwidths, by an isochronous resource manager on the bus.
Figure 9.2 shows an example situation where two isochronous channels are allocated.
These have a guaranteed bandwidth, and any remaining bandwidth is used by pending asyn-
chronous transfers. Thus isochronous traffic takes some priority over asynchronous traffic.
By comparison, asynchronous transfers are sent to explicit addresses on the 1394 bus
(Figure 9.3). When data is to be sent, it is preceded by a destination address, which each
node checks to identify packets for itself. If a node finds a packet addressed to itself, it copies
it into its receive buffer. Each node is identified by a 16-bit ID, containing the 10-bit bus ID
and 6-bit node or physical ID. The actual packet addressing, however, is 64 bits wide, pro-
viding a further 48 bits for addressing a specific offset within a node's memory. This ad-
dressing conforms to the control and status register (CSR) bus architecture standard. The
ISO/IEC 13213:1994 minimises the amount of circuitry required by 1394 ICs to interconnect
with standard parallel buses. The 48-bit offset allows for the addressing of 256 terabytes of
memory and registers on each node.
Timing indicator
Timing indicator
Isochronous channel
#1 time slot
Isochronous channel
#1 time slot
Isochronous channel
#2 time slot
Isochronous channel
#2 time slot
Time slot available for
asynchrono us trans port
Time slot available for
asynchrono us trans port
Packet frame = 125
Packet frame = 125
s
s
µ
µ
Figure 9.2
Bandwidth allocation on the IEEE-1394 bus
