Motherboard Design - Computer Busses - page 130

VCRs, cameras, TVs, and so on. It also has an optional ATI-ImpactTC NSTC/PAL encoder
which provides a TV output for the graphics accelerators.

5.2.4 DRAM interface
The DRAM interface is a 64-bit data path that supports fast page mode (FPM) and extended
data out (EDO) memory. The integrated DRAM controller supports from 4 MB to 256 MB of
main memory. The 12 multiplexed address lines (MA[11:0]) allow the chips to support 4-bit,
16-bit and 64-bit memory, both symmetrical and asymmetrical addressing. The MTXC has
six RAS lines which enables support to up to six rows of DRAM (the TXC has eight RAS
lines).
The MTXC supports SRAM. The 14 multiplexed address lines (MA[13:0]) allow the
MTXC to support 16-bit and 64-bit SDRAM devices. The MTXC has six CS (chip select)
lines (muxed into RAS[5:0]) which allows six rows of the faster SDRAM modules to be in-
stalled.
All these memory types FPM, EDO and SDRAM can be mixed on the 430TX (but only
the FPM and EDO are supported in the 430HX board). The extra lines that have been added
in the MTXC are:

• SRAS [A,B] - SRAM row address strobe.

• SCAS [A,B] - DRAM column address.

5.2.5 Second- level cache
The MTXC supports cache memory area of 64 MB using either 8 K · 8 or 16 K · 8 SRAM
blocks to store the cache tags for either 256 KB or 512 KB SRAM cache. (8 K · 8 is used for
256 KB and 16 K · 8 is used for 512 KB). Each cache entry is 32 bits (4 bytes) thus the total
cache memory size is 512 KB (16 K · 8 · 4). The signals are:

CCS Cache chip select - set active upon power-up and allows access to the

cache.

TWE Tag write enable - allows new state and tag addresses to be written into

the cache.

COE Cache output enable - puts the cache data onto the data bus.

GWE Global write enable - causes all bytes to be written to.

CADS Cache address strobe - cache loads the address register from the ad-

dress pins.

CADV Cache advance - the address is automatically increment to the next

word.

Tag address - input lines for tag addresses. TIO[7 : 0]

. Cache chip select - KRQAK specifies DRAM cache, else implements a

64 MB main memory cache.

KRQAK/ CS4_64

BWE

Byte write enable - enables up to eight bytes from the data bus.

Figure 5.10 shows the interface between the MTXC and the second-level cache. Note that
four 32 K · 32 devices make up the 512 KB (4 · 32 · 4) SRAM cache. Only two are shown in
Figure 5.10, as the other two are connected in parallel with the two shown.