Information Technology Reference
In-Depth Information
16K
·
8 Tag RAM
MTXC
TIO[7:0]
TWE#
D[7:0]
WE#
OE#
HA[18:5]
A[13:0]
32K
·
32 SRAM
HCLK]
CLK
A[14:0]
OE#
CS1#
ADSC#
ADV#
ADSP#
CS2
CS2#
GWE#
BWE#
BE[3:0]#
HA[17:3]
COE#
CCS#
CADS#
CADV#
ADS#]
HA18
GND]
D[31:24]
D[23:16]
D[15:8]
D[7:0]
HD[63:56]
HD[55:48]
HD[47:40]
HD[39:32]
GWE#
BWE#
HBE[7:4]#
D[31:24]
D[23:16]
D[15:8]
D[7:0]
HD[31:24]
HD[23:16]
HD[15:8]
HD[7:0]
GWE#
BWE#
BE[3:0]#
HBE[3:0]#
Figure 5.10
Second-level cache interface
Cache control register (CC)
This is an 8-bit register which is located at 52h in the I/O memory. It defines secondary
cache operations. Its format is:
Bit
Description
7:6
Secondary cache size - 00 (disabled), 01 (256K), 10 (512K), 11 (reserved).
5:4
SRAM cache type - 00 (pipelined burst SRAM), 01 (reserved), 10 (re-
served), 11 (two banks of pipelined burst).
3
NA disable - 1 (disable), 0 (enabled); normally enabled.
2
Reserved.
1
Secondary cache force miss or invalidated (SCFMI). When set to a 1, the
Level 2 hit/miss facility is disabled, else it is enabled.
0
First-level cache enable (FLCE) - 1 (enable), 0 (disable). When it is set to a
1, the control responds to processor cycles with KEN# active. Normal
mode for FLCE, SCFMI is 1, 0.
Extended cache control register (CEC)
This is an 8-bit register which is located at 53h in the I/O memory. It defines the refresh rate
for DRAM Level 2. Its format is:
