CAN Basic Architectures - CAN System Engineering - page 20

is performed on the falling edge (from recessive to dominant ) of a Start Of Frame
bit. This edge defines the beginning of a CAN frame; the BTL restarts at Sync_
Seg .
• “Soft” (re-)synchronization is performed within a CAN frame at edges from re-
cessive to dominant ; it lengthens or shortens single bits of that frame.
If the CAN bus level changes outside of Sync _ Seg , the distance between Sync _ Seg
and that edge is called the Phase_Error . When a Phase_Error is detected, it is com-
pensated by synchronization. In case of a resynchronization, Phase_Seg1 is extend-
ed (when the edge was between Sync_Seg and the Sample Point ) or Phase_Seg2 is
shortened (when the edge was between the Sample Point and the next Sync_Seg ).
This is intended to keep the distance between the edge of the input signal and the
following Sample Point at the configured value. In a hard synchronization, the
Phase_Error will be fully eliminated, while a single resynchronization will reduce
the Phase_Error only by an amount of up to the value of the (Re-)Synchronization
Jump Width ( SJW ). A residual error ( Phase_Error - SJW ) may remain until the next
synchronization.
There may be at most one synchronization between two Sample Points . The dis-
tance between the edge and Sample Point , which is maintained by synchronizations,
allows the CAN bus level time to stabilize and filters out spikes that are shorter
than ( Prop_Seg + Phase_Seg1 ). Internal delay in the CAN transceiver, from the
transceiver's transmit input to its receive output, may cause transmitters to see all
their transmitted edges “late”, this happens especially at high bit rates. Therefore, to
avoid lengthening their own transmitted dominant bits, transmitters do not synchro-
nize on “late” edges. The bit-stuffing mechanism guarantees a maximum distance
of ten bits between two edges for synchronization inside a frame. Phase_Errors
caused by clock tolerances will accumulate between synchronizations, so a receiv-
er's actual Sample Point position (relative to the transmitter's Sample Point ) may
need to be corrected. The size of the Phase Buffer around the Sample Point defines
how large a Phase_Error can be tolerated and therefore limits the clock tolerance.
Figure 1.9 shows how the phase buffer segments are used to compensate for
Phase_Errors . Two successive bit times are presented: At the top with a synchroni-
zation to a “late” edge, which is detected between Sync_Seg and the Sample Point ,
in the centre without synchronization (as reference) and at the bottom with a syn-
chronization to an “early” edge, which is seen after the Sample Point .
The examples in Fig. 1.10 show how short dominant spikes on the CAN bus are
filtered out by the BTL . In both examples, the spike starts at the end of Prop_Seg
and has a length of less than ( Prop_Seg + Phase_Seg1 ).
In the first example, SJW is at least as large as the Phase_Error of the “late” edge
which starts the spike. Therefore, the Sample Point can be moved past the end of
the spike. At the Sample Point , the CAN bus is returned to recessive and the spike
is suppressed.
In the second example, SJW is smaller than the Phase_Error of the edge which
starts the spike. The Sample Point cannot be shifted far enough; the dominant spike
at the Sample Point is taken as actual bus level.