Civil Engineering Reference
In-Depth Information
Fig. 1.8
Bit timing
•
Phase_Seg1
: [1…8]
•
Phase_Seg2
: [1…8]
•
SJW
: [1…4]
•
BRP
: [1…32]
In most CAN implementations, the sum of (
Prop_Seg
+
Phase_Seg1)
is collected
(as
TSEG1
) together with
Phase_Seg2
(as
TSEG2
) in a first configuration register,
while
SJW
and
BRP
are collected in a second register. It should be noted that the
values programmed into these bit timing registers are—for each of
TSEG1
,
TSEG2
,
SJW
and
BRP—
the formal values reduced by one; hence, the values are written
[0…n - 1] instead of [1…n]. This allows, for example, to represent SJW (actual
range [1…4]) by only two bits. When
Prop_Seg
and
Phase_Seg1
are configured as
a sum,
Prop_Seg
may be even larger than 8 while
Phase_Seg1
will be correspond-
ingly shorter.
Therefore, the length of a bit time is (programmed values) [
TSEG1
+
TSEG2
+ 3]
tq or (formal values) [
Sync_Seg
+
Prop_Seg
+
Phase_Seg1
+
Phase_Seg2
] tq.
The sequential flow of the bit time and possible synchronizations are controlled
by the CAN protocol controller's
BTL
, a state machine that is evaluated once per
time quantum
. The
BTL
has the task to evaluate the CAN bus level and to determine
the position of the
Sample Point
. The remaining part of the CAN protocol control-
ler, the Bit Stream Processor (BSP) state machine, is evaluated only once per bit
time, at the
Sample Point
, with the CAN bus level evaluated at the
Sample Point
taken as the sampled bit value.
1.2.6.1
“Hard” and “Soft” Synchronization
At each time quantum, the CAN controller's
BTL
compares the actual level of
the CAN bus with the stored value of the last
Sample Point
, to detect edges for
synchronization.
There are two types of synchronization:
• “Hard” synchronization
