Real-Time Analysis of Human Body Parts and Gesture-Activity Recognition in 3D - 3D Modeling and Animation: Synthesis and Analysis Techniques for the Human Body - page 163

Inter-Stage-Level Parallelism and Pipeline Architecture
The above discussions are about the available data independencies. There is
another parallelism resulting from the data flow structure. The algorithm stages
of the low-level processing part form a pipelined process. A corresponding
architecture is a pipelined multi-processor architecture (Figure 21). Figure 22
shows the projected performance of such architecture. Series 1 shows the
throughput when communication cost is zero, while in series2 the communication
cost is 20% of the computation cost. The additional benefit of such architecture
over other parallel architecture is that the processor can be tailored to the
requirement of the stage. For example, the CPU used to process background
elimination does not have to carry a floating-point unit. The limiting factor of such
architecture is the granularity of the stages. When a stage counts more than 50%
of the overall computation time, the speed-up is limited.
Figure 21. Macro-pipeline architecture.
Figure 22. Throughput of pipelined architecture.