Real-Time Analysis of Human Body Parts and Gesture-Activity Recognition in 3D - 3D Modeling and Animation: Synthesis and Analysis Techniques for the Human Body - page 162

Figure 19. Symmetric parallel architecture.
isms are thread or process-level parallelisms. SMT (Simultaneous Multithreading)
and CMP (single chip multi-processor) architectures can exploit process-level
parallelism. However, the SMT architecture does not seem to be a good choice
for this parallelism, since the almost identical threads will content the same
resource and do not increase the functional unit utilization over the single thread
model. Thus, we propose using CMP architecture, or even separate chip
processors, to exploit such inter-frame parallelism. A proposed architecture is
shown in Figure 19.
Figure 20 shows the projected performance change on such parallel architec-
tures, where series1 is the performance under the assumption that communica-
tion cost is negligible, while series2 is the performance change where the
communication cost is 20.
Figure 20. Performance of symmetric architecture.