SIGNAL SOURCES FOR SIMULATION, TESTING, AND CALIBRATION - Design and Development of Medical Electronic Instrumentation - page 262

Figure 6.10 This simple yet versatile arbitrary waveform generator can be programmed from the
printer port of a PC. Once loaded with an array of digital data, this arb acts as a stand-alone instru-
ment capable of delivering two simultaneous analog signals, each with an amplitude resolution of
12 bits, and variable temporal resolution down to 50 ns (20 megapoints/s).

When triggered rather than continuous cycling through the waveform is desired, fl ip-

fl flop IC14 is allowed to control IC1's enable line by way of switch SW1. In the triggered

mode, the op's *Q output goes low when enabled by the rising edge of a trigger pulse

presented to its clock input line. This state is maintained until reset at the end of the wave-
form cycle by the same reset pulse that zeroes the counter chain. In this mode, trigger
ambiguity is less than one clock cycle.
Downloading and uploading RAM waveform data from and to the PC is done through
the printer port under a simple serial protocol implemented in the software available in
the accompanying CD-ROM. On the Arb, the chain of 74LS323 ICs (IC16-IC19) of
Figure 6.13 forms a 32-bit serial-to-parallel and parallel-to-serial converter. When the
remote mode of operation is selected by the computer (digital low on bit 1 of the output
port of the printer port), LOC/*REM goes low, causing IC20 to transfer control of the
clock (CLK), address generator reset (*RESET), RAM output-enable (*OE), and RAM
write (*WR) to the lines of the printer port. The mode control lines (pins 1 and 19) of the
74LS323s select between hold, shift left, shift right, and parallel load of the bits of the
chain's 32-bit register. Data are clocked serially into IC16 and shifted down the chain
toward IC19 by each rising edge of the serial clock line (SCLK). Once a complete 32-bit
word is positioned in the register of the chain, IC16-IC19 drive the RAM data bus, and a
write strobe is used to store the register's contents in the current address. The address gen-
erator is then advanced, and the cycle is repeated to store successive waveform data points.
Data can be read from the RAM into the computer by reversing this process. Once an
address is selected, data can be loaded from the RAM data bus into the register formed by

fl ip- fl