Biomedical Engineering Reference
In-Depth Information
by logic signals during that clock period: path delays, setup and latchup times, logic gate
propagation delays, and skew. As clock frequencies increase, the time left over for logical
computation decreases, up to the point that skew often causes system failures due to
incomplete processing during a clock cycle.
For this reason, PCB tracks that distribute the clock must be tuned so that the delay
from the clock driver to each load is the same. Whenever possible, the loading on each
track carrying the clock should be the same, and in this case skew is minimized by mak-
ing all tracks the same length. For unbalanced loads, delay times can be tuned through
RC
terminations or by careful adjustment of the track lengths.
Crosstalk and Vulnerable Paths
Crosstalk is the noise induced into a track by the presence of a pulse stream in an adjacent
track. In essence, crosstalk is EMI caused by the product on itself. The amount of crosstalk
is a
ected by track spacing, routing, signal direction, and grounding. The major problem
with crosstalk arises when the voltages induced on a quiet line are su
ff
cient to be detected
as a change in logic state by the receivers of that line. In high-speed systems, the capacitive
and inductive coupling between lines is considerable, and crosstalk must be reduced
through appropriate design.
First, proper transmission line termination reduces the amount of radiated energy from a
driven track, and spurious emissions that nevertheless escape can be shielded through the
use of grounded guards. This design consideration is particularly important for lines driven
with high-voltage, high-current, and high-frequency signals. Floating lines connected to high-
impedance receivers are notably sensitive to crosstalk, and proper shielding, as well as main-
taining them at a distance from possible radiating tracks, must be ensured. In addition, it is
possible to see from transmission line theory that crosstalk between two adjacent tracks is
minimized if the two signals
flow in the same direction.
The analysis should be extended to identifying potential coupling paths between signal
lines and RFI sources (including ESD) and then taking steps to minimize them through
proper placement of PCB tracks and components. For example, shields can be reinforced
where transformers and heat sinks are placed, the areas of loops formed by PCB tracks
should be minimized, and magnetic coupling paths should be oriented orthogonally.
Finally, remember that components, connectors, and mounting parts that can be
accessed from the outer world are very often the paths of entry into a device's circuit for
EMI and especially for ESD. Even an exposed metallic screw on an otherwise insulating
panel can make it possible for unwanted signals to get into the circuit and cause interference.
Common panel-mounted vulnerable parts include membrane keyboards, LEDs, potentiome-
ters, connectors, and switches, together with their mounting hardware.
fl
Analysis of Circuit Board Performance
Although you may consider such tools as a time-domain re
ectometer or an RF network ana-
lyzer as belonging strictly to a communications lab, these can aid considerably in the design
of circuit boards for high-speed and high-immunity applications. These tools are capable of
measuring the actual impedances, time delays, and complex re
fl
cients of a cir-
cuit. These measurements often show that calculations of these parameters result in very
crude estimates that have to be improved on for good circuit performance. In most cases, the
iterative process of design will require building and evaluating a test board to determine if
the original design considerations were e
fl
ection coe
ective. This test board is usually not populated
with the actual active components, but the PCB tracks, passive components, sockets, and
connectors, as well as the terminated dummy IC packages, form a network of transmission
lines that can be analyzed with con
ff
fi
dence.
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