Cryptography Reference
In-Depth Information
r_in
r_out
Combinational logic
Data input
n
0
CLK
Data output
Fig. 18.1
Basic loop architecture
of an algorithm, for example in one byte during a particular round of an instantiation
of block cipher, which is commonly done in theoretical fault analysis.
A schematic with the basic loop architecture is shown in Fig.
18.1
. The CLK signal
denotes the clock signal. The r_in signal represents the input of the data register and
equals the output of the combination logic used to compute the cipher. The r_out
signal represents the output of the data register and is the value stored in the register.
The fault injection mechanism for inserting a clock glitch is described in Fig.
18.2
for
a normal clock with a glitch. During normal operation, as shown in Fig.
18.2
a, all the
intervals of the positive edges for each clock are longer than the maximum delay of the
circuit and are correctly stored in an intermediate state in the data register. If a glitch
occurs in the clock signal during the computation and the shortened interval is shorter
than the maximum delay of the circuit, as shown in Fig.
18.2
b, the value stored in the
data register r_in is likely to become corrupted due to a timing violation. Therefore,
we can inject a fault into the desired intermediate state during the computation of an
algorithm in the targeted device if we can generate a glitch at the appropriate time.
18.3 Experimental Environments for Fault Injection
In this section, we explain the methods for generating a clock glitch and targeting
devices and algorithms with fault injection.
18.3.1 Developed Experimental Environment
Precise control of the timing of a clock glitch is important for investigating the
relationship between the shortened interval and the injected fault. To achieve this,
we developed an experimental environment based on the following concepts.
•
Use two clock sources for which we control their phases in order to be able to
generate a clock glitch with precise timing.
