Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 48

assigned to all variables, or a default condition must be used and all variables must be assigned
default values outside the conditional block. The correct way of coding is depicted here:
always @*
begin
out_a = 2 ' b00;
out_b = 2 ' b00;
if (sel==2 ' b00)
begin
out_a = 2 ' b01;
out_b = 2 ' b10;
end
else if (sel == 2 ' b01)
out_a = 2 ' b01;
else
out_a = 2 ' b00;
end
Here is the code showing the correct use of case statements:
always @*
begin
out_a = 2 ' b00;
out_b = 2 ' b00;
case (sel)
2 ' b00:
begin
out_a = 2 ' b01;
out_b = 2 ' b10;
end
2 ' b01:
out_a = 2 ' b01;
default:
out_a = 2 ' b00;
endcase
end
2.6.4.11 Loop Statements
Loop statements are used to execute a block of statements multiple times. Four types of loop
statement are supported in Verilog: forever , repeat , while and for . The statement
forever continuously executes its block of statements. The remaining three statements are
commonly used to execute a block of statements a fixed number of times. Their equivalence is shown
below. For repeat :
i=0;
repeat (5)
begin
$display("i=%d\n", i);
i=i+1;
end