Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 40

initial
begin

always
begin

procedural assignment 1
procedural assignment 2
procedural assignment 3

procedural assignment 1
procedural assignment 2
procedural assignment 3

end end

Figure 2.11 Initial and always blocks

An always block is synthesizable provided it adheres to coding guidelines for synthesis. From the
perspective of its execution in a simulator, an always block behaves like an initial block
except that, once it ends, it starts repeating itself.

2.6.4.2 Blocking and Non-blocking Procedural Assignments

All assignments in a procedural block are called procedural assignments. These assignments are of
two types, blocking and non-blocking. A blocking assignment is a regular assignment inside a
procedural block. These assignments are called blocking because each assignment blocks the
execution of the subsequent assignments in the sequence. In RTLVerilog code, these assignments
are used to model combinational logic. For the RTL code to infer combinational logic, the blocking
procedural assignments are placed in an always procedural block.
There are several ways of writing what is called the sensitivity list in an always block. The
sensitivity list helps the simulator in effective management of simulation. It executes an always
block only if one of the variables in the sensitivity list changes. The classical method of sensitivity
listing is to write all the inputs in the block in a bracket, where each input is separated by an 'or' tag.
Verilog-2001 supports comma-separated sensitivity lists. It also supports just writing a ' ' for the
sensitivity list. The simulator computes the list by analyzing the block by itself.
The code in Figure 2.12 illustrates the use of a procedural block to infer combinational logic in
RTL Verilog code. The always block contains two blocking procedural assignments. The
sensitivity list includes the two inputs x and y , which are used in the procedural block. A list
of inputs x and y to these assignments are placed with the always statement. This list is the
sensitivity list. This procedural block once synthesized will infer combinational logic. The three
methods of writing a sensitivity list are shown in Figure 2.12.
It should also be noted that, as the left-hand side of a procedural assignment must be of type reg ,
so sum and carry are defined as variables of type reg .
In contrast to blocking procedural assignments, non-blocking procedural assignments do not
block other statements in the block and these statements execute in parallel. The simulator executes
this functionality by assigning the output of these statements to temporary variables, and at the end of
execution of the block these temporary variables are assigned to actual variables.