Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 39

Table 2.12 Equality operators

Operator type Operator symbol Operation performed

Equality ¼¼ Equality

! ¼ Inequality

¼¼¼ Case equality

! ¼¼ Case Inequality

Example 2.8
While comparing A ¼ 4 0 b101x and B ¼ 4 0 b101x using ¼¼ and ¼¼¼ , out ¼ (A ¼¼ B) will

be x and out ¼ (A ¼¼¼ B) will be 1 (Table 2.12).

2.6.4 Behavioral Level
The behavioral level is the highest level of abstraction in Verilog. This level provides high-level
language constructs like for , while , repeat , if - else and case . Designers with a software
programming background already know these constructs.
Although the constructs are handy and very powerful, the programmer must know that each
construct inRTLVerilog infers hardware. High-level constructs are very tempting to use, but the HW
consequence of their inclusion must be well understood. For example, for loop to a software
programmer suggests a construct that simply repeats a block of code a number of times, but if used in
RTL Verilog the code infers multiple copies of the logic in the loop. There are behavioral-level
synthesis tools that take a complete behavioral model and synthesize it, but the logic generated using
these tools is usually not optimal. The tools are not used in those designs where area, power and
speed are important considerations.
Verilog restricts all the behavioral statements to be enclosed in a procedural block. In a procedural
block all variables on the left-hand side of the statements must be declared as of type reg , whereas
operands on the right-hand side in expressions may be of type reg or wire .
There are two types of procedural block, always and initial .

2.6.4.1 Always and Initial Procedural Blocks
Aprocedural block contains one or multiple statements per block. An assignment statement used in a
procedural block is called a procedural assignment. The initial block executes only once,
starting at t ¼ 0 simulation time, whereas an always block executes continuously at t ¼ 0 and

repeatedly thereafter.
The characteristics of an initial block are as follows.

. This block starts with the initial keyword. If multiple statements are used in the block, they are
enclosed within begin and end constructs, as shown in Figure 2.11.
. This block is non-synthesizable and non-RTL. This block is used only in a stimulus.
. There are usually more than one initial blocks in the stimulus. All initial blocks execute
concurrently in arbitrary order, starting at simulation time 0.
. The simulator kernel executes the initial block until the execution comes to a #delay
operator. Then the execution is suspended and the simulator kernel places the execution of this
block in the event list for delay - time units in the future.
. After completing delay - time units, the execution is resumed where it was left off.