Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 541

s 1 s 2

s 0 h 1 h 2

h 0

= = = =

= =

row 0

h 1 s 0 h 2 s 1 h 3 s 2

row 1

iteration

h 2 s 0 h 3 s 1 h 4 s 2

row 2

.
.
.
.

h 7 s 0 s 0 s 1 s 1 s 2

row 7

(b)

pointer length

Figure 13.20 (Continued)

columns 4, 5 and 6 are considered for the next iteration. If all three characters are matched, then
columns 5 and 6 are considered for the next iteration. If no match is found, the architecture
implements six iterations of the algorithm in parallel. The table also highlights the sharing that is
performed across iterations.
Figure 13.23 shows the architecture that implements thesemultiple iterations. The selection block
finally selects the appropriate answer based on the results of the multiple iterations.

13.3.3 Encryption
The encryption block takes source encoded data as clear text and ciphers the text using a pre-stored
key. AES is the algorithm of choice for most digital communication applications. The algorithm is
very regular and designed for hardware mapping. A representative architecture for moderate data
rate applications is described below.

13.3.3.1 AES Algorithm

An AES algorithm encrypts a 128-bit block of plain text using one of three sizes of key, 128, 192 or
256 [31]. The encryption is performed in multiple rounds. For the three key sizes the number of
rounds for data encryption are n ¼ 10, 12 and 14. In the key scheduling stage, the key is expanded to