Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 522

Using techniques explained in earlier chapters, this chapter develops time-shared, dedicated and
parallel architectures for different building blocks in a communication transmitter. MATLAB code
is listed for the design. A critical analysis is usually required for making major design decisions. The
communication system design gives an excellent example to illustrate how different design options
should be used for different parts of the algorithm for effective design.
A crucial step in designing a high-end digital system is the top-level architecture, so this chapter
first gives design options and then covers each of the building blocks in detail. For different
applications these blocks implement different algorithms. For example, the source encoding may
compress voice, video or data. The chapter selects one algorithm out of many options, and gives
architectural design options for that algorithm for illustration.

13.2 Top-Level Design Options
The advent of software-defined radios has increased the significance of top-level design. A high
data-rate communication systemusually consists of hybrid components comprising ASICs, FPGAs,
DSPs and GPPs. Most of these elements are either programmable or reconfigurable at runtime. A
signal processing application in general, and a digital communication application in particular,
requires sequential processing of a stream of data where the data input to one block is processed and
sent to the next block for further processing. The algorithm that runs in each block has different
processing requirements.
There are various design paradigms used to interconnect components. These are shown in
Figure 13.1.

13.2.1 Bus-based Design
In this design paradigm, all the components are connected to a shared bus. When there are many
components and the design is complex, the system is mapped as a system-on-chip (SoC). These
components are designed as processing elements (PEs). A shared bus-based design then connects all
the PEs in an SoC to a single bus. The system usually performs poorly from the power consumption
perspective. In this arrangement, each data transfer is broadcast. The long bus has a very high load

Mem 0

GPP mem 0 RF

mem 0

GPP RF

GPP DSP 0 DSP 1 RF mem

DSP 0

mem 1 DSP 0 DSP

DSP 1

mem 1

(a) (b) (c)

Figure 13.1 Interconnection configurations. (a) Shared bus-based design. (b) Peer-to-peer connections.
(c) NoC-based design