Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 521

13
Digital Design of Communication
Systems
13.1 Introduction
This chapter covers the methodology for designing a complex digital system, and an example of a
communication transmitter is considered.
Major blocks of the transmitter are the source coding block for voice or data compression, forward
error correction (FEC) for enabling error correction at the receiver, encryption for data security,
multiplexing for adding multiple similar channels in the transmitted bit stream, scrambling to avoid
runs of zeros or ones, first stage of modulation that packs multiple bits in a symbol and performing
phase, frequency, amplitude or a hybrid of these modulations, and digital up-conversion (DUC) to
translate a baseband modulated signal to an intermediate frequency (IF). This digital signal at IF is
passed to a digital-to-analog (D/A) converter and then forwarded to an analog front end (AFE) for
processing and onward transmission in the air.
The receiver contains the same components, cascaded together in reverse order. The receiver first
digitizes the IF signal received from its AFE using an A/D converter. It then sequentially passes the
digital signal to a digital down-converter (DDC), demodulator, descrambler, demultiplexer,
decryption, FEC decoder and source decoder blocks. All these blocks re-do whatever transforma-
tions are performed on the signal at the transmitter.
Receiver design, in general, is the more challenging because it has to counter the noise introduced
on the signal on its way from the transmitter. Also, the receiver employs components that are running
at its own clock, and frequency synthesizers that are independent of the transmitter clock, so this
causes frequency, timing and phase synchronization issues. Multi-path fading also affects the
received signal. All these factors create issues of carrier frequency and phase synchronization, and
frame and symbol timing synchronization. The multi-path also adds inter-symbol interference.
For high data-rate communication systems most of the blocks are implemented in hardware
(HW). The algorithms for synchronizations in the receiver require complex nested feedback loops.
The transmitter example in this chapter uses a component-based approach. This approach is also
suitable for software-defined radios (SDRs) using reconfigurable field-programmable gate arrays
(FPGAs) where precompiled components can be downloaded at runtime to configure the
functionality.