Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 30

While running a simulation inVerilog the designer may encounter a variable taking a combination
of the above values at different bit locations. In binary representation, the following is an example of
a number containing all four possible values:
20 0 b 0011_1010_101x_x0z0_011z
The underscore character (_) is ignored by Verilog simulators and synthesis tools and is used
simply to give better visualization to a long string of binary numbers.
2.5.5 Data Types
Primarily there are two data types in Verilog, nets and registers.
2.5.5.1 Nets
Nets are physical connections between components. The net data types are wire , tri , wor ,
trior , wand , triand , tri0 , tri1 , supply0 , supply1 and trireg . An RTLVerilog code
mostly uses the wire data type. A variable of type wire represents one or multiple bit values.
Although this variable can be used multiple times on the right-hand side in different assignment
statements, it can be assigned a value in an expression only once. This variable is usually an output of
a combinational logic whereas it always shows the logic value of the driving components. Once
synthesized, a variable of type wire infers a physical wire.
2.5.5.2 Registers
A register type variable is denoted by reg . Register variables are used for implicit storage as values
should be written on these variables, and unless a variable is modified it retains its previously
assigned value. It is important to note that a variable of type reg does not necessarily imply a
hardware register; it may infer a physical wire once synthesized. Other register data types are
integer , time and real .
AVerilog simulator assigns 'x' as the default value to all uninitialized variables of type reg .If
one observes a variable taking a value of 'x' in simulation, it usually traces back to an uninitialized
variable of type reg .
2.5.6 Variable Declaration
In almost all software programming languages, only variables with fixed sizes can be declared. For
example, in C/C þþ a variable can be of type char , short or int . Unlike these languages, a
Verilog variable can take any width. The variable can be signed or unsigned. The following syntax is
used for declaring a signed wire:
wire signed [ < range > ] < net_name >< net_name > *;
Here * implies optional and the range is specified as [Most Significant bit (MSb): Least
Significant bit (LSb)] . It is read as MSb down to LSb. If not specified, the default value of the
range is taken as one bit width. A similar syntax is used for declaring a signed variable of type reg :
reg signed [ < range > ] < reg_name >< reg_name > *;