Micro-programmed Adaptive Filtering Applications - Digital Design of Signal Processing Systems: A Practical Approach - page 470

mem A mem B

32 32

16 16 16 16

TDR 2 TDR 3

TDR 0 CR 1 CR 0

x n

x n-1

x n-2 h 1

h 0

x n-3

TDR 1

X X X X

+ +

ACC 1 ACC 0

Figure 11.12 Two MAC blocks and specialized registers for maximum data reuse

11.6.2.4 Program Sequencer

The program sequencer handles four types of instruction: next instruction in the sequence, branch
instruction, repeat instruction, and subroutine instruction.

11.6.2.5 Repeat Instruction

A detailed design of a loop machine is given in Chapter 10. The machine supports four nested loop
instruction. The format of a loop instruction is given here.

repeat LABEL COUTN

The instructions following the loop instruction marks the start of the loop and the address of this
instruction is stored in Loop Start Address (LSA) register. Address of the LABEL marks the address
of the last instruction in the loop and the address is stored in Loop End Address (LEA) register. The
COUNT gives the number of times the zero overhead loop needs to be repeated and the value is stored
in Loop Counter (LC) register. The logic that loop machine implements is given here

if (PC == LEA && LC !=0)
next_address = LSA;
LC --;
else
next_address = PC ++;

The accelerator also supports a special repeat with single instruction in the loop body. For this
repeat instruction, IR and PC are disabled for any update and the instruction in the IR register is
executed COUNT number of cycles before the registers are released for any updates. The format of
the repeat signal instruction is given here

repeat1 COUNT
Instruction