Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 22

2.2 About Verilog
2.2.1 History
Philip Moorby invented Verilog in1983/84. At that time he was with Gateway Design Automation.
VHDL is another language used for designing hardware. It was with the advent of synthesis tools by
Synopsys in1987 when Verilog and VHDL started to change the whole paradigm and spectrum of
hardware design methodology. Within a few years, HDLs became the languages of choice for
hardware design. In 1995, Open Verilog International (OVI) IEEE-1364 placed Verilog in the public
domain to compete with VHDL [4].
It was critical for Verilog to keep pace with the high densities predicted byMoore's Law. Now the
average process geometries are shrinking and billion-transistor chips are designed using 45-nm and
smaller nanometer technologies.
The Verilog standard is still evolving. More and more features and syntax are being added that, on
one hand, are providing higher level of abstraction, and on the other hand are helping the test
designer to effectively verify an RTL design. Most of this advancement has been steered by the
IEEE. Following the release of IEEE standard 1364-1995, in 1997 the IEEE formed another working
group to add enhancements to the existing Verilog standard. The new standard was completed in
2001, and this variant of the language is called Verilog-2001 [5]. It provides additional support,
flexibility and ease of programming to developers.
In 2001, a consortium (Accellara) of digital design companies and electronic design automation
(EDA) tool vendors set up a committee to work on the next generation of extensions to Verilog. In
2003, the consortium released SystemVerilog 3.0, without ratification. In 2004, it released System-
Verilog 3.1 [6] which augmented in Verilog-2001 many features that facilitated design and
verification. In 2005, while still maintaining two sets of standards, the IEEE released Verilog-
2005 [7] and SystemVerilog-2005 [8], the latter adding more features for modeling and verification.
2.2.2 What is Verilog?
Verilog is a hardware description language. Although it looks much like C, it is not a software
programming language. It is very important for the Verilog programmer to understand hardware
concepts. Each line of Verilog code in the design means one or more components in hardware.
Verilog is rich in constructs and functionality. Some of the constructs are specific to supporting
verification and modeling and do not synthesize to infer hardware. The synthesis is performed using
a synthesis tool, which is a compiler that translates Verilog into a gate-level design. The synthesis
tool understands only a subset of Verilog, the part of Verilog called 'RTL Verilog'. All the other
constructs are 'non-RTL Verilog'. These constructs are very helpful in testing, verification and
simulation.
It is imperative for the designer toknowat the register transfer levelwhat is beingcoded in the design.
The RTL signifies the placement of registers in the design and the flowof data among the registers. The
complete Verilog is a combination of RTL and non-RTL constructs. A good hardware designer must
have sound understanding of these differences and comprehensive command of RTL Verilog
constructs. The programmer must also have a comprehension of the design to be coded inRTLVerilog.
Advancements in technology are allowing designers to realize ever more complex designs, posing
real challenges for testing and verification engineers. The testing of a complex design requires
creativity and ingenuity. Many features specific to verification are being added in SystemVerilog,
which is a companion standard supported bymost of the Verilog tool vendors. Verilog also provides a
socket-level interface, known as 'programming language interface' (PLI), to be used with other