Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 21

2

Using a Hardware Description
Language

2.1 Overview
This chapter gives a comprehensive coverage of Verilog and SystemVerilog. The focus is mostly on
Verilog, which is a hardware description language (HDL).
The chapter starts with a discussion of a typical design cycle in implementing a signal processing
application. The cycle starts with the requirements specification, followed by the design of an
algorithm using tools like MATLAB . To facilitate partitioning of the algorithm into hardware
(HW) and software (SW), and its subsequent mapping on different platforms, algorithm design and
coding techniques inMATLAB are described. TheMATLAB code has to be structured so that the
algorithm developers, SW designers and HWengineers can correlate various components and can
seamlessly integrate, test and verify the design and can return to the original MATLAB
implementation if there are any discrepencies in the results.
The chapter then has a brief account of Verilog. As there are several textbooks available on
Verilog [1-3], this chapter focuses primarily on design and coding guidelines and relevant rules.
There is a particular emphasis on coding rules for keeping synthesis in perspective. A description of
'register transfer level' (RTL) Verilog is presented. RTL signifies the placement of registers in
hardware while keeping an account of the movement of data among these registers.
SystemVerilog adds more features for modeling and verification. AlthoughVerilog itself provides
constructs towrite test benches for verification, it lacks features that are required to verify a complex
design. Traditionally verification engineers have resorted to other languages, such as Vera or e, or
have used a 'program language interface' (PLI) to interface Verilog code with verification code
written in C/C

. The use of PLI requires complex interface coding. SystemVerilog enhances
some of the features of Verilog for hardware design, but more importantly adds powerful features
that facilitate verification of more complex designs. Assertion, interface, package, coverage and
randomization are examples of some of these features.

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