Overview - Digital Design of Signal Processing Systems: A Practical Approach - page 18

echo needs to be cancelled before the near-end speech is compressed and packetized for transmis-
sion on an IP network. An LEC processing element is designed to implement line echo cancellation.
The LEC processing also detects double talk and updates the coefficients of the adaptive filter only
when line echo is present in the signal and the near end is silent. There is an extended discussion of
LEC and its implementation in Chapter 11.
Each processing element in the SoC is scheduled to perform a series of tasks for each channel.
These tasks for a particular channel are periodically assigned to a set of PEs. Each PE keeps checking
the task list, while it is performing the currently assigned task. Finding a new task in the task list, the
PE programs a channel of the DMA to bring data and context for this task into on-chipmemory of the
processor. Similarly, if the processor finds that it is tasked to perform an algorithm where it also
needs to bring the program into its programmemory (PM), the PE also requests the DMA to fetch the
code for the next task in the PM of the PE. This code fetching is kept to a minimum by carefully
scheduling the tasks on the PEs that already have programs of the assigned task in its PM.
1.8.3 Design Flow Migration
As explained earlier, usually the communication system requires component-level integration of
different devices to implement digital baseband, RF transmitter and receiver, RF oscillator and
power management functionality. The advancement in VLSI technology is now enabling the
designer to integrate all these technologies on the same chip.
Although the scope of this topic is limited to studying digital systems, it is very pertinent to point
out that, owing to cost, performance and power dissipation considerations, the entire system
including the analog part is nowbeing integrated on a single chip. This design flowmigration is show
in Figure 1.15. The ASICs and microcontroller are incorporated as intellectual property (IP) cores
and reconfigurable logic (RL) of the FPGAs is also placed on the same chip. Along with digital
components, RF and analog components are also integrated on the same chip. For example, a mixed-
signal integrated circuit for a mobile communication system usually supports ADC and DAC for on-
chip analog-to-digital and digital-to-analog conversion of baseband signals, phase-locked loops
(PLLs) for generating clocks for various blocks, and codec components supporting PCM and other
Figure 1.15 Mixed-signal SoC integrating all components on a multi-chip board on a single chip