Unfolding and Folding of Architectures - Digital Design of Signal Processing Systems: A Practical Approach - page 344

generate a folded architecture that maps theDFGon fewer hardware computational units. The folded
architecture with the schedule can then be easily implemented using, respectivly, a datapath
consisting of computational nodes and a controller based on a finite state machine. The chapter
gives examples to illustrate the methodology. These examples are linked with their implementation
as state machine-based architecture.
8.2 Unfolding
Design decisions are based on the ratio of sampling and circuit clock speeds. The sampling clock is
specific to an application and is based on Nyquist sampling criteria or band-pass sampling
techniques [1-3]. These sampling rates lower-bound the sampling clock. The sampling clock also
imposes a throughput constraint on the design. In many applications the samples are also passed to a
digital-to-analog (D/A) converter. On the other hand, the circuit clock depends on several factors,
such as the target technology and power considerations. In many high-throughput applications, the
main focus of the design is to run the circuit at the highest achievable clock rate. If fully dedicated
architecture (FDA) mapping of a dataflow graph on to hardware cannot be synthesized at the
required clock rate, the designer must look for other options.
Unfolding increases the area of the design without affecting the throughput. A slower clock does
effect the power dissipation but increases the area of the design. The area-power tradeoff must be
carefully studied if the unfolding is performed with the objective of power reduction. The unfolding
transformation is very effective if there are more registers in the original DFG that can be effectively
retimed for reducing the critical path delay of the design. This is especially true if the design is
mapped on an FPGAwith embedded computational units. These units have fixed number of registers
that can be effectively mapped in an unfolded design. Similarly for feedback designs, the timing
performance of the design can be improved by first adding and retiming pipeline registers and then
applying the unfolding transformation to evenly distribute the registers with replicated functional
units. It is important to point out that in many design instances pipelining and retiming is usually the
option of choice because it results in less area than an unfolded design [4].
8.3 Sampling Rate Considerations
As the sampling and circuit clocks dictate the use of unfolding and folding transformations, it is
important to understand the requirements placed on the sampling clock. This section explains
Nyquist and band-pass sampling criteria.
8.3.1 Nyquist Sampling Theorem and Design Options
For digitization of an analog signal, the Nyquist sampling theorem defines the minimum constraint
on the sampling frequency of the analog signal. The sampling frequency defines the number of
samples the system needs to process every second. For perfect reconstruction, the Nyquist sampling
criterion constrains the minimum sampling rate to be greater than or equal to twice the maximum
frequency content in the signal:
f s 2 f N
where f s and f N represent sampling frequency and maximum frequency content in the analog signal,
respectively.