Digital Signal Processing Reference
In-Depth Information
7.4.4 C-slow for an Instruction Set Processor
C-slow can be applied to microprocessor architecture. The architecture can then run a multi-
threaded application where C threads are run in parallel. This arrangement does require a careful
design of memories, register files, caches and other associated units of the processor.
7.5 Look-ahead Transformation for IIR filters
Look-ahead transformation (LAT) can be used to add pipeline registers in an IIR filter. In a simple
configuration, the technique looks ahead and substitutes the expressions for previous output values
in the IIR difference equation. The technique will be explained using a simple example of a
difference equation implementing a first-order IIR filter:
y½¼ay n
1
½
þx½
ð
7
:
6
Þ
Using this expression, y[n
1] can be written as:
yn
1
½
¼ay n
2
½
þxn
1
½
ð
7
:
7
Þ
On substituting (7.7) in (7.6) we obtain:
2
y½¼a
yn
2
½
þax n
1
½
þx½
This difference equation is implemented with two registers in the feedback loop as compared to one
in the original DFG. Thus the transformation improves the IPB. These registers can be retimed for
better timing in the implementation. The original filter, transformed filter and retiming of the
registers are shown in Figure 7.28.
The value of y[n
2] can be substituted again to add three registers in the feedback loop:
3
2
y½¼a
yn
3
½
þa
xn
2
½
þax n
1
½
þx½
In general, M registers can be added by repetitive substitution of the previous value, and the
generalized expression is given here:
M
1
y½¼a
M
ynM
0
a
i
x½ni
½
þ
ð
7
:
8
Þ
i¼
y[n]
x[n]
x[n]
y[n]
+
+
x[n
]
+
y[n]
+
+
X
X
X
X
X
a
2
a
a
2
a
(a)
(b)
(c)
Figure 7.28
Look-ahead transformation. (a) Original first-order IIR filter. (b) Adding one register in the
feedback path using look-ahead transformation. (c) Retiming the register to get better timing
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