Digital Signal Processing Reference
In-Depth Information
7.4.2 C-slow for Block Processing
The C-slow technique works well for block processing algorithms. C blocks from a single stream
of data can be simultaneously processed by the C-slow architecture. A good example is AES
encryption where a block of 128 bits is encrypted. By replicating every register in an AES
architecture, with C registers the design can simultaneously encrypt C blocks of data.
7.4.3 C-slow for FPGAs and Time-multiplexed Reconfigurable Design
As FPGAs are rich in registers, the C-slow technique can effectively use these registers to process
multiple streams of data. In many designs the clock frequency is fixed to a predefined value, and the
C-slow technique is then very useful to meet the fixed frequency of the clock.
C-slow and retiming can also be used to convert a fully parallel architecture to a time-multiplexed
design where C partitions can be mapped on run-time reconfigurable FPGAs. In a C-slow design,
as the input is only valid at every Cth clock, retiming can move the registers to divide the design into
C partitions where the partitions can be optimally created to equally divide the logic into C parts.
The time-multiplexed design requires less area and is also ideal for run-time reconfigurable logic.
Figure 7.27 shows the basic concept. The DFG of (a) is 2-slowed as shown in (b). Assuming all the
three nodes implement some combinational logic, that is repeated twice in the design. The design
is retimed to optimally place the registers while creating two equal parts. The C-slowed and retimed
design is given in Figure 7.27(c). This DFG can now be mapped on time-multiplexed logic, where
the data is fed into the design at one clock cycle and the results are saved in the registers. These values
are input to the design that reuses the same computational nodes so C-slow reduces the area.
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Figure 7.27
C-slow technique for time-multiplexed designs. (a) Original DFG with multiple nodes
and few registers and large critical path. (b) Retimed DFG. (c) The DFG partitioned into two equal sets of
logic where all the three nodes can be reused in a time-multiplexed design
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