Digital Signal Processing Reference
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a 0
b 0
s 0
CC0
c 0
a 1
b 1
s0 1
c0 1
s 1
c 1
MUX
CC1
s1 1
c1 1
a 2
b 2
s0 2
c0 2
CC2
s1 2
c1 2
s0 3
MUX
s 2
s 3
c0 3
MUX
a 3
b 3
s0 3
c0 3
CC3
s1 3
c1 3
s1 3
c1 3
c 3
MUX
a 4
b 4
s0 4
c0 4
CC4
s 4
s1 4
c1 4
MUX
c out
Figure 7.14 Pipelining a 5-bit conditional sum adder (CSA)
 
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