Digital Signal Processing Reference
In-Depth Information
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CPA
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Figure 7.13
(a) Optimized implementation of 3-coefficient direct-formFIR filter. (b) Possible locations
to apply cut-set pipelining to a compression tree
7.2.9 Pipelining Carry Propagate Adder
Some of the CPAs are very simple to pipeline as the logic levels in their architectures are aligned and
all paths from input to output run in parallel. The conditional sum adder (CSA) is a good example
where cut-set lines can be easily placed for adding pipeline registers, as shown in Figure 7.14. For
other CPAs, it is not trivial to augment pipelining. An RCA, as discussed in earlier examples,
requires careful handling to add pipeline registers, as does a carry generate adder.
7.2.10 Retiming Support in Synthesis Tools
Most of the synthesis tools do support automatic or semi-automatic retiming. To get assistance in
pipelining, the user can also add the desired number of registers at the input or output of a
feedforward design and then use automatic retiming to move these pipeline registers to optimal
places. In synthesis tools, while setting timing constraints, the user can specify a synthesis option
for the tool to automatically retime the registers and place them evenly in the combinational logic.
The Synopsys design compiler has a balance_registers option to achieve automatic retiming [7].
This option cannot move registers in a feedback loop and some other restrictions are also applicable.
7.2.11 Mathematical Formulation of Retiming
One way of performing automatic retiming is to first translate the logic into a mathematical
model [2] and then apply optimization algorithms and heuristics to optimize the objectives set in the
model [4, 5]. These techniques are mainly used by synthesis tools and usually a digital designer does
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