Overview - Digital Design of Signal Processing Systems: A Practical Approach - page 11

1.5.2 Implementation
When the design has been described at RTL level, its implementation is usually a straightforward
translation in a hardware description language (HDL) program. The program is then synthesized for
mapping on an FPGA or ASIC implementation.

1.5.3 Verification
As the number of gates on a single silicon device increases, so do the challenges of verification.
Verification is also critical in VLSI design as there is hardly any tolerance for bugs in the hardware.
With application-specific integrated circuits, a bug may require a re-spin of fabrication, which is
expensive, so it is important for an ASIC to be 'right first time'. Even bugs found in FPGA-based
designs result in extended design cycles.

1.6 Competing Objectives in Digital Design

To achieve an effective design, a designer needs to explore the design space for tradeoffs of
competing design objectives. The following are some of the most critical design objectives the
designer needs to consider:

area

.

critical path delays

.

testability

.

power dissipation. .

The art of digital design is to find the optimal tradeoff among these. These objectives are
competing because, for example, if the designer tries to minimize area then the design may result
in longer critical paths and may also affect the testability of the design. Similarly, if the design as
synthesized for better timing means shorter critical paths, the design may result in a larger area.
Better timing also means more power dissipation, which depends directly on the clock frequency.
It is these competing objectives that make learning the techniques covered in this topic very
pertinent for designers.

1.7 Synchronous Digital Hardware Systems
The subject of digital design has many aspects. For example, the circuit may be synchronous or
asynchronous, and it may be analog or digital. A digital synchronous circuit is always an option of
choice for the designer. In synchronous digital hardware, all changes in the system are controlled by
one or multiple clocks. In digital systems, all inputs/outputs and internal values can take only
discrete values.
Figure 1.8 depicts an all-digital synchronous circuit in which all changes in the system are
controlled by a global clock clk . A synchronous circuit has a number of registers, and values in
these registers are updated at the occurrence of positive or negative edges of the clock signal. The
figure shows positive-edge triggered registers. The output signal from the registers R 0 and R 1 are fed
to the combinational logic. The signal goes through the combinational logic which consists of gates.
Each gate causes some delay to the input signal. The accumulated delay on each pathmust be smaller
than the time period of the clock, because the signal at the input of R 2 register must be stable before