Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 297

Exercises
Exercise 6.1

Convert the following expression into its equivalent 8-bit fixed-point representation:

y½n¼ 0 : 231 x½nþ 0 : 396 x½n 1 þ 0 : 1111 x½n 5

Further convert the fixed-point constants into their respective CSD representations. Consider x[n]is
an 8-bit input in Q1.7 format. Draw an RTL diagram to represent your design. Each multiplication
should be implemented as a CSDmultiplier. Consider only the four most significant non-zero bits in
your CSD representation.

Exercise 6.2

Implement the following difference equation in hardware:

y½n¼ 0 : 9821 y½n 1 þx½n

First convert the constant to appropriate 8-bit fixed-point format, and then convert fixed-point
number in CSD representation. Implement CSD multipliers and code the design in RTL Verilog.

Exercise 6.3

Draw an optimal architecture that uses a CSD representation of each constant with four non-zero
bits. The architecture should only use one CPA outside the filter structure of Figure 6.26.

x ] y n

+

x
b

+ x

a

+

x
c

Figure 6.26 Design for exercise 6.3

Exercise 6.4

Optimize the hardware design of a TDF FIR filter with the following coefficients in fixed-point
format:

h½n¼½ 3 13 219 221

Minimize the number of adder levels using sub-graph sharing and CSE techniques.