Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 270

x[n] x[n-4] x[n-8]

x[n-2] x[n-6]

x

x x x

x

h 0 h 4

h 1 h 2 h 3

y[n]

+

+ + + +

0

(a)

x n

h 4 h 3 h 2 h 1 h 0

x x x x x

+ + + +

y n

critical path

(b)

Figure 6.8 (a) Pipeline direct-formFIRfilter best suited for implementation on FPGAs withDSP48-like
building blocks. (b) TDF structure for optimal mapping of multipliers as CSD shift and add operation

multiplication by non-constant values. For many applications requiring multiplication by constants,
CSD multiplication usually is the most optimal option.
Retiming is an effective technique to systematically move algorithmic delays in a design to reduce
the critical path of the logic circuit. In Chapter 7, retiming is applied to transform the filter given in
Figure 6.8(a) to get an equivalent filter shown in Figure 6.8(b). This new filter is the transposed direct
form[6]. It is interesting to observe that in this form, without adding pipelining registers, the algorithm
delays are systematicallymoved using retiming transformation from the upper edge of the DFG to the
lower edge. This has resulted in reducing the critical path of an L-coefficient FIR filter from one
multiplier and L 1 adders of direct form to one multiplier and an adder as shown in Figure 6.8(b).

In FDA designs of a TDF FIR filter, each constant in the multiplier is converted to CSD representation
and then appropriate PPs are generated for non-zero digits in CSD representation of the coefficients.
These PPs are reduced by carry save reduction to two layers. The outputs of these two layers are
respectively stored in two registers. Although this doubles the number of registers in the design, it
removes CPAs which otherwise are required to add the final two layers into one for each coefficient
multiplication. Figure 6.9 shows the TDF FIR filter implemented as CSD multiplication and carry save
addition. Eachmultiplier represents the generation of PPs for non-zero digits in CSD representation of the
coefficients and their reduction to two layers using the carry save reduction scheme.
The critical path can be further reduced by adding pipeline layers in the design, as shown
in Figure 6.10(a). Inserting appropriate levels of pipelining can reduce the critical path to just