Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 269

// Adding all the PPs with GCV
// The design to be implemented as Wallace or Dadda
reduction scheme
yn_v = pp[0]+pp[1]+pp[2]+pp[3]+
pp[4]+pp[5]+
pp[6]+pp[7]+pp[8]+pp[9]+
pp[10]+pp[11]+
pp[12]+pp[13]+pp[14]+pp[15]+gcv;
end
endmodule
module stimulusFIRfilter;
reg signed [15:0] X;
reg CLK;
wire signed [31:0] YN, YNCV, YNCSD;
integer i;
// Instantiating all the three modules for equivalency checking
FIRfilterCV FIR_CV(X, CLK, YNCV);
FIRfilterCSD FIR_CSD(X, CLK, YNCSD);
FIRfilter FIR(X, CLK, YN);
initial
begin
CLK = 0;
X=1;
#1000 $finish;
end
// Generating clock signal
always
#5 CLK = CLK;
// Generating a number of input samples
initial
begin
for (i=0; i<256; i=i+1)
#10 X = X+113;
end
initial
$monitor ($time, " X=%h, YN=%h, YNCSD=%h, YNCV=%h\n",
X, YN<<1, YNCSD, YNCV);
endmodule
6.6.3 Transposed Direct-form FIR Filter
The direct-form FIR filter structure of Figure 5.5 results in a large combinational cloud of reduction
tree and CPA. The cloud can be pipelined to reduce the critical path delay of the design.
Figure 6.8(a) shows a 5-coefficient FIR filter, pipelined to reduce the critical path delay of the
design. Now the critical path consists of a multiplier and an adder. Pipelining causes latency and
a large area overhead in implementing registers. This pipeline FIR filter can be best mapped on the
Vertix -4 and Vertix -5 families of FPGAs with embedded DSP48 blocks. The effectiveness of
this mapping is demonstrated in Chapter 5.
In many design instances, using general-purpose multipliers of DSP48 blocks may not be
appropriate as they are a finite resource and should be used for parts of the algorithm that require