Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 257

1

1 1 1

1 1 1 1 1

1 1 1

1 1 1 1 1

1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1

Figure 6.1 CV calculation

perspectives, a CPA is one of the most expensive building blocks in HW implementation. In FDA
implementation, simple transformations are applied to minimize the use of CPAs.
Figure 6.3(a) shows the DFG mapping of (6.1). If implemented as it is, the critical path of the
design consists of one multiplier and one adder. Section 6.4 showed the design for FDA by using
a compression tree that reduces all the PPs consisting of terms for CSD multiplication, x[n] and CV
for sign extension elimination. The design then uses a CPA and reduces the two layers from the

0 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1

0 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1

1

Figure 6.2 Use of the Wallace tree for PP reduction to two layers