Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 256

Here the constant in the equation is transformed toCSD representation by recursively applying the
string property on the binary representation of the number:

16'b 0111 0101 0011 1111
0111 0101 0100 0001
1001 0101 0100 0001
2 0

2 3 þ 2 5 þ 2 7 þ 2 9 2 15

The CSD representation of the constant thus reduces the number of non-zero digits from 11 to 6.
For multiplication of 0.916 with y[n 1] in FDA implementation thus requires generating only

6 PPs. These PPs are generated by appropriately shifting y[n 1] by weight of the bits in Q1.15
format representation of the constant as CSD digits. The PPs are:

y½n 1 y½n 1 2 3 þ y½n 1 2 5 þ y½n 1 2 7 þ y½n 1 2 9 y½n 1 2 15

1] by 0,3,5,7,9 and 15 and adding or
subtracting these PPs according to the sign of CSD digits at these locations. The architecture can be
further optimized by incorporating x[n] as the seventh PP and adding CV for sign extension
elimination logic as the eighth PP in the compression tree. All these inputs to the compression tree
are mathematically shown here:

The PPs are generated by hardwired right shifting of y[n

y½n¼y½n 1 y½n 1 2 3 þ y½n 1 2 5 þ y½n 1 2 7 þ y½n 1 2 9 y½n 1 2 15 þx½nþCV

The CV is calculated by adding the correction for multiplication by 1 and 1 in the CSD
representation of the number. The CV calculation follows the method given in Chapter 5. For
multiplication by 1 the CV is computed by flipping the sign bit of the PP and adding 1 at the location
of the sign bit and then extending the number by all 1s. Whereas for multiplication by 1 the PP is
generated by taking the one's complement of the number. This sign extension and two's complement
in this case require flipping of all the bits of the PP except the sign bit, adding 1 at the locations of the
sign bit and the LSB, and then extending the number by all 1s. Adding contribution of all the 1s from
all PPs gives us the CV:

1110 1010 1011 1111 0010 0000 0000 001

Figure 6.1 shows the CV calculation. The filled dots show the original bits and empty dots show
flipped bits of the PPs. Now these eight PPs can be reduced to two layers of partial sums and carries
using any compression method described in Chapter 5.
Figure 6.2 shows the use of Wallace tree in reducing the PPs to two. Finally these two layers are
added using any fast CPA. The compression is shown by all bits as filled dots.

6.5 Optimized DFG Transformation

Several architectural optimization techniques like carry save adder (CSA), compression trees and
CSD multipliers can be used to optimize DFG for FDA mapping. From the area and timing