Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 249

Figure 5.55 Bit array for Dadda reduction

Exercise 5.6

Add the following two numbers using conditional sum addition techniques:

1001_1101

1101_1011

Exercise 5.7

Design and code in RTLVerilog a 16-bit conditional sum adder with two stages of pipeline (add one
register to break the combinational cloud). Assume C_in is not known prior to addition.

Exercise 5.8

Multiply a 5-bit signed multiplicand a with a 5-bit unsigned multiplier b by applying a sign-
extension elimination technique, compute the correction vector for multiplication. Use the
computed correction vector to multiply the following:

a ¼ 11011
b ¼ 10111

Exercise 5.9

Reduce the bit array shown in Figure 5.55 using a Dadda reduction scheme. Specify the number of
FAs and HAs required to implement the scheme.

Exercise 5.10

Design and draw (using dot notation) an optimal logic to add twenty 1-bit numbers. Use a Dadda
reduction tree for the compression.