Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 248

18 18-bit multipliers and DSP48 blocks. Select the option in the synthesis tool to use these blocks.

Compare your results for better timing and area.

Exercise 5.2

Design an 8-coefficient FIR filter and use a pipelined structure that optimally utilizes DSP48 blocks
of Xilinx families of FPGAs. Write RTLVerilog code of the design. Synthesize the design with and
without pipelining options to show the improvements.

Exercise 5.3

Perform appropriate mathematical transformation to effectively use compression trees to map the
following equation:

f ¼ aþ ð 2 b Þ cþð Þ e :

Assume a, b, c, d and e are signed numbers inQ3.2, Q3.2, Q1.3, Q2.4 and Q1.3 formats, respectively.
Use a Wallace reduction scheme for compression and draw the design logic in dot notation. Use the
following numbers to verify the design:

a ¼ 5 0 b 011 10

b ¼ 5 0 b 111 01
c ¼ 4 0 b 0 101

6 0 b d ¼ 01 1100

4 0 b e ¼ 0 011

Exercise 5.4

Design an optimal hardware to implement the following equation:

d ¼ abc
where a, b and c are in Q4.4, Q3.5 and Q2.6 format unsigned complex numbers, respectively. Verify
your design for a

j3.32. First convert these
numbers in specified Q format and then design the logic, showing compression trees as blocks in the
design.

¼ 11.5 þ j4.23, b ¼ 2.876 þ j1.23 and c ¼ 1.22 þ

Exercise 5.5

Design a 32-bit hybrid adder that combines different adder blocks. Use 4-bit RCA, 8-bit CSA, 8-bit
conditional sumadder, 8-bit Brent-Kung and 4-bit of carry look-ahead adders in cascade.Write RTL
Verilog code of the design and synthesize your design on any Spartan -3 family of FPGAs. Now
design different 32-bit adders exclusively using the above techniques. Synthesize all the adders on
the same FPGA and compare your results for area and timing.