Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 217

3 N 3 N 3 N N 3 N N N N N N

b N − 1: a − 1 : b − 1 :

a N − 1: b − 1 : a − 1:

4 4 4 2 4 2 2 4 2 4

N N

a − 1:0 b −1:0

4 4

0

0

0

N/4-bit adder N/4-bit adder N/4-bit adder

C i n

1 1

1

N/4-bit adder

N/4-bit adder N/4-bit adder

N/4-bit adder

N /4+1

N/4+1 N/4+1 N/4 N/4 N/4+1 N/4

1 0 C N/4

1 0

Mux

Mux

C N/2

1 0

Mux

N/4

N/2+1

Cout

N N N N

s

s N − 1 : s − 1: − 1 : 0

2 2 4 4

Figure 5.21 Hierarchical CSA

5.5.11 Using Hybrid Adders
A digital designer is always confronted with finding the best design option in area-power-time
tradeoffs. A good account of these tradeoffs is given in [10]. The designer may find it appropriate to
divide the adder into multiple groups and use different adder architecture for each group. This may
help the designer to devise an optimal adder architecture for the design. This design methodology is
discussed in [10] and [11].

5.6 Barrel Shifter
A single-cycle N-bit logic shifter implementing , where s is a signed integer number, can be

implemented by hardwiring all the possible shift results as input to a multiplexer and then using s to
select the appropriate option at the output. The shifter performs a shift left operation for negative
values of s. For example, x 2 implies a shift left by 2.
The design of the shifter is shown in Figure 5.22(a), where x is the input operand and all possible
shifts are pre-performed as input to the MUX and s is used as a select line to the MUX. The figure
clearly shows that, for negative values of s, its equivalent positive number will be used by the MUX
for selecting appropriate output to perform a shift left operation.
The design can be trivially extended to take care of arithmetic along with the logic shifts. This
requires first selecting either the sign bit or 0 for appropriately appending to the left of the operand for
shift right operation. For shift left operation, the design for both arithmetic and logic shift is same.
When there are not enough redundant sign bits, the shift left operation results in overflow. The design
of an arithmetic and logic shifter is given in Figure 5.22(b).
Instead of using one MUX with multiple inputs, a barrel shifter can also be hierarchically
constructed. This design can also be easily pipelined. The technique can work for right as well as for
left shift operations. For

x s

, the technique works by considering s as a two's complement signed
number where the sign bit has negative weight and the rest of the bits carry positiveweights. Moving

x s