Digital Signal Processing Reference
In-Depth Information
input cin;
output c_out;
output [15:0] sum;
wire c4, c8, c8_0, c8_1, c12_0, c12_1, c16_0, c16_1, c16L2_0, c16L2_1;
wire [15:4] sumL1_0, sumL1_1;
wire [15:12] sumL2_0, sumL2_1;
// Level one of hierarchical CSA
assign {c4,sum[3:0]} = a[3:0] + b[3:0] + cin;
assign {c8_0, sumL1_0[7:4]}= a[7:4] + b[7:4] + 1'b0;
assign {c8_1, sumL1_1[7:4]}= a[7:4] + b[7:4] + 1'b1;
assign {c12_0,sumL1_0[11:8]}= a[11:8] + b[11:8] + 1'b0;
assign {c12_1,sumL1_1[11:8]}= a[11:8] + b[11:8] + 1'b1;
assign {c16_0, sumL1_0[15:12]}= a[15:12] + b[15:12] + 1'b0;
assign {c16_1, sumL1_1[15:12]}= a[15:12] + b[15:12] + 1'b1;
// Level two of hierarchical CSA
assign c8 = c4 ? c8_1 : c8_0;
assign sum[7:4] = c4 ? sumL1_1[7:4]: sumL1_0[7:4];
// Selecting sum and carry within a group
assign c16L2_0 = c12_0 ? c16_1 : c16_0;
assign sumL2_0 [15:12] = c12_0? sumL1_1[15:12] : sumL1_0[15:12];
assign c16L2_1 = c12_1 ? c16_1 : c16_0;
assign sumL2_1 [15:12] = c12_1? sumL1_1[15:12]: sumL1_0[15:12];
// Level three selecting the final outputs
assign c_out = c8 ? c16L2_1 : c16L2_0;
assign sum[15:8] = c8 ? {sumL2_1[15:12], sumL1_1[11:8]} :
{sumL2_0[15:12], sumL1_0[11:8]};
endmodule
b[3:0]
a[3:0]
b[15:12] a[15:12]
b[11:8]
a[11:8]
b[7:4]
a[7:4]
C
0
4 bit Ripple
Carry Adder
C
0
4 bit Ripple
Carry Adder
C
0
4 bit Ripple
Carry Adder
C
0
4 bit Ripple
Carry Adder
0
0
0
0
C
1
4 bit Ripple
Carry Adder
C
1
4 bit Ripple
Carry Adder
C
1
4 bit Ripple
Carry Adder
C
1
4 bit Ripple
Carry Adder
1
1
1
1
C
in
C
out
4 bit 2-to-1 Mux
4 bit 2-to-1 Mux
4 bit 2-to-1 Mux
4 bit 2-to-1 Mux
C[12]
C[8]
C[4]
S[15:12]
S[11:8]
S[7:4]
S[3:0]
Figure 5.20
A 16-bit uniform-groups carry select adder
Search WWH ::
Custom Search