Digital Signal Processing Reference
In-Depth Information
appropriate bits in each group by the LSC is shown with a diagonal line. The LSC from each group
determines which one of the two bits in the next column will be brought down to the next level of
processing. If the LSC is 0, the upper two bits of the next column are selected, otherwise the lower
two bits are selected for the next level. For the second group, the sum bit of the first column is also
dropped down to the next level. The LSCs in the first level are shown with bold fonts. Finally in the
next level the two groups formed in the previous level are merged and the LSC selects one of the two
3-bit group to the next level. In this example, as the LSC is one, it selects the lower group.
Example: The conditional sum adder technique will be further illustrated using a 16-bit addition.
Figure 5.18 shows all the steps in computing the sum of two 16-bit numbers. Figure 5.19 lays out the
architecture of the adder. At level 0, 16 CCs compute sum and carry bits assuming carry-in 0 and 1.
a
i
b
i
a
i
1
0
0
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
0
1
1
0
b
i
Group sum and block carry out
Group
width
Group
carry-in
i
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
s0
i
1
0
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
0
c0
i
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
1
0
s1
i
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
c1
i
1
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
2
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
1
1
4
0
0
0
1
1
1
1
0
1
0
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
0
0
1
1
8
0
0
1
1
1
0
1
0
0
0
0
1
0
1
1
0
1
0
0
0
0
1
0
1
0
0
0
1
1
16
0
0
1
Figure 5.18
Example of a 16-bit conditional sum adder
Search WWH ::
Custom Search