Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 208

P[i]= p[i] & P[i-1];
G[i]= g[i] | (p[i] & G[i-1]) ;
end
end
always@(*)
begin
//Generate all carries and sum
c[0]=c_in;
for(i=0;i<N;i=i+1)
begin
c[i+1] = G[i] | (P[i] & c[0]);
sum[i] = p[i] ^ c[i];
end
c_out = c[N];
end
endmodule
module stimulus;
reg [15:0] A, B;
reg CIN;
wire COUT;
wire [15:0] SUM;
integer i, j, k;
BinaryCarryLookaheadAdder #16 BCLA(A, B, CIN, SUM, COUT);
initial
begin
A=0;
B=0;
CIN = 0;
#5 A= 1;
for (k=0; k<2; k=k+1)
begin
for (i=0; i<5; i=i+1)
begin
#5A=A+1;
for (j=0; j<6; j=j+1)
begin
#5 B = B+1;
end
end
CIN=CIN+1;
end
#10 A = 16'hFFFF; B=0; CIN = 1;
end
initial
$monitor ($time, " A=%d, B=%d, CIN=%b, SUM=%h, Error=%h,
COUT=%b\n", A, B, CIN, SUM, SUM-(A+B+CIN), COUT);
endmodule