Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 204

C 0

a 0

s 3 a 3 b 3 s 2 a 2 b 2 s 1 a 1 b 1 s 0 b 0

c 2

c 3 c 1

Adder Adder Adder Adder

g 3

g 2 g 1 p 0 g 0

p 3 p 2 p 1

Carry Look Ahead Logic CLA 00

P 0 G 0

s 6 a 6 a 5 s 4 a 4

s 7 a 7 b 7 b 6 s 5 b 5 b 4

c 7 c 6 c 5

c 4

Adder Adder Adder Adder

g 7 p 6 g 6 g 5 g 4

p 7 p 5 p 4

CLA 01

P 1 G 1

s 11 a 11

b 11 s 9 a 9 b 9

s 10 a 10 b 10 s 8 a 8 b 8

c 11 c 10 c 9 c 8

Adder

Adder Adder

Adder

g 11 p 10 g 10 p 9 g 9 p 8 g 8

p 11

CLA 02

P 2 G 2

s 14 a 14 b 14 s 13 a 13 b 13 s 12 a 12 b 12

s 15 a 15 b 15

c 13 c 12

c 15 c 14

Adder Adder Adder Adder

p 15 g 15 p 14 g 14 p 13 g 13 p 12 g 12

CLA 03

P 3 G 3

CLA 10

Figure 5.11 A 16-bit carry look-ahead adder using two levels of CLA logic