Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 203

Industrial practice is to use 4 -bit wide blocks. This limits the computation of carries until c 3 , and
c 4 is not computed. The first four terms in c 4 are grouped as G 0 and the product p 3 p 2 p 1 p 0 in the last
term is tagged as P 0 as given here:

c 4 ¼ g 3 þp 3 g 2 þp 3 p 2 g 1 þp 3 p 2 p 1 g 0 þp 3 p 2 p 1 p 0 c 0

Let:

G 0 ¼ g 3 þp 3 g 2 þp 3 p 2 g 1 þp 3 p 2 p 1 g 0

P 0 ¼ p 3 p 2 p 1 p 0

Now the group G 0 and P 0 are used in the second level of the CLA to produce c 4 as:
c 4 ¼ G 0 þP 0 c 0

Similarly, bits 4 to 7 are also grouped together and c 5 , c 6 and c 7 are computed in the first level of the
CLA block using c 4 from the second level of CLA logic. The first-level CLA block for these bits also
generates G 1 and P 1 .
Figure 5.11 shows a 16-bit adder using four carry look-ahead 4-bit wide blocks in the first level. Each
block also computes its G and P using the same CLA as used in the first level. Thus the second level
generates all the carries c 4 , c 8 and c 12 required by the first-level CLAs. In this way the design is hierarchically
broken down for efficient implementation. The same strategy is further extended to build higher order
adders. Figure 5.12 shows a 64-bit carry look-ahead adder using three levels of CLA logic hierarchy.

5.5.6 Hybrid Ripple Carry and Carry Look-ahead Adder
Instead of hierarchically building a larger carry look-ahead adder usingmultiple levels of CLA logic,
the carry can simply be rippled between blocks. This hybrid adder is a good compromise as it yields
an adder that is faster than RCA and takes less area than a hierarchical carry look-ahead adder. A
12-bit hybrid ripple carry and carry look-ahead adder is shown in Figure 5.13.

5.5.7 Binary Carry Look-ahead Adder
The BCLAworks in a group of two adjacent bits, and then fromLSB toMSB successively combines
two groups to formulate a new group and its corresponding carry. The logic for the carry generation
of an N-bit adder is:

g i ¼ a i b i ð 5 9a Þ

:

p i ¼ a i b i ð 5 9b Þ

:

ðG i ; P i Þ¼ðg i ; p i Þðg i 1 ; p i 1 Þ...ðg 1 ; p 1 Þðg 0 ; p 0 Þ ð 5 9c Þ

:

The problem can be solved recursively as:

ðG 0 ; P 0 Þ¼ðg 0 ; p 0 Þ

for i ¼ 1to N 1

ðG i ; P i Þ¼ðg i ; p i ÞðG i 1 ; P i 1 Þ
c i ¼ G i þP i c 0

end