Digital Signal Processing Reference
In-Depth Information
Input [1:4]
Carry out
LUT/RAM
4
Carry &
Control
Logic
Output
Control
Q Output
Flip-flop /
Latch
Clock, enable, set/reset
Carry in
3
(a)
Cout
SHIFT IN
+
LUT: A B
ORCY
SOPOUT
SOP IN
0
YBMUX
YB
Dual-Port
Shift-Reg
LUT
RAM
ROM
MUXCY
0 1
G4
G3
A4
A3
A2
A1
WG4
WG3
WG2
WG1
WS DI
+
+
B
Y= A B Cin
GYMUX
A
P
WG4
WG3
WG2
WG1
XORG
DY
FF
LATCH
D
Q
Q
ALT DIG
G2
PROD
G1
BY
DYMUX
Y
MULIAND
0
CE
CLK
CE
CK
SR REV
BY
SR
SHIFTOUT
DIG
Dedicated Carry logic
WSG
WE [2:0]
WE
CLK
SLICEWE[2:0]
1 half-Slice = 1bit-adder
MUXCY
0 1
WSF
CE
Shared
between
x & y
Registers
CLK
Cin
SR
(b)
Figure 5.9
(a) Fast-carry logic blocks. (b) Fast-carry logic in Vertix
-II pro FPGA slice. (c) One CLB
of Vertix
-II pro inferring two 4-bit adders, thus requiring four CLBs to implement a 16-bit adder. (d) A
64-bit RCA using fast-carry chain logic (derived from Xilinx documentation)
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