Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 198

begin
a_r<=a;
b_r<=b;
cin_r<=cin;
s_r<=s;
cout_r<= cout;

end
endmodule

-II pro,
then the synthesis tool will infer this logic for fast propagation of the carry signal across the adder.
AVertix

If the code is synthesized for an FPGA that supports fast carry chain logic, like Vertix

-II pro FPGA consists of a number of configurable logic blocks (CLBs), and each CLB
has four 'slices'. Each slice further has two look-up tables (LUTs) and dedicated logic to compute
generate (g) and propagate (p) functions. These functions are used by the synthesis tool to infer carry
logic for implementing a fast RCA. The equations of g i and p i and logic it uses for generating fast
carry-out c i þ 1 in a chain across an RCA are:

c iþ 1 ¼ g i þp i c i

p i ¼ a i b i

g i ¼ a i b i

This is shown in Figures 5.9(a) and (b). When the Verilog code of this section is synthesized on the
device, the synthesized design uses fast carry logic in cascade to tie four CLBs in a column to
implement a 16-bit RCA. The logic of 16-bit and 64-bit adders is shown in Figures 5.10(c) and (d),
respectively.

5.5.4 Fast Adders
If not mapped on an FPGAwith fast carry chain logic, an RCA usually is the slowest adder as each
full adder requires carry-out from the previous onefor its sum and carry-out computation. Several
alternative architectures have been proposed in the literature. All these architectures somehow
accelerate the generation of carries for each stage. This acceleration results in additional logic. For
FGPA implementation the designer needs to carefully select a fast adder because some have carry
acceleration techniques well suited for FPGA architectures while others do not. As already
discussed, an RCA makes the most optimal use of carry chains, although all the full adders need
to fit in a column for effective use of this logic. This usually is easily achieved. ACSA also replicates
RCA blocks, so each block still makes an effective use of fast carry chain logic with some additional
logic for the selection of one sum out of two sums computed in parallel.

5.5.5 Carry Look-ahead Adder
A closer inspection of the carry generation process reveals that a carry does not have to depend
explicitly on the preceding carries. In a carry look-ahead adder the carries entering all the bit
positions of the adder are generated simultaneously by a carry look-ahead (CLA) generator; that is,
computation of carries takes place in parallel with sumcalculation. This results in a constant addition
time independent of the length of the adder. As the word length increases, the hardware organization