Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 173

are resetable using a global rst_n signal. It is important to ensure that for a synchronous DFG that
implements a streaming application, a new sample to the DFG is fed in every sample clock cycle. The
design must be constructed in a manner that all the nodes in the DFG complete their respective
executions before the arrival of the next sample clock. Even for the dynamic node, the worst-case
conditionmust be considered and the designmust guarantee completion before the arrival of the next
sample clock. All the nodes that can do so start and execute in parallel. Nodes A, B and C execute in a
sequence, and D and E work in parallel and use the output of C from the previous iteration. If x, the
execution of time of dynamic node D, is bounded by 10, then the execution of D and E takes a
maximum of 19 circuit clocks, whereas nodes A, B and C take 16 clocks. Thus the circuit clock
should be at least 19 times faster than the sampling clock.
Exercises
Exercise 4.1
The code below lists one iteration of an algorithm implementing a block in a digital communications
receiver. The algorithm processes a complex input InputSample and gives it a phase correction.
The phase correction is computed in this code. Draw DFG, and map it on to an FDA. Write RTL
Verilog code of the design using 16-bit fixed point arithmetic.Write a stimulus to verify the RTL code.
Mixer_out = InputSample*(-j*Phase);
// a number of algorithmic registers
Mixer_Out[2] = Mixer_Out[1];
Mixer_Out[1] = Mixer_Out[0];
Mixer_Out[0] = Mixer_out;
Delayline[2] = Delayline[1];
Delayline[1] = Delayline[0];
// feedback loop, where a and b are arrays of 16-bit constants
// Kp and Ki are also 16-bit constant numbers
Delayline[0]= - Delayline[1]*a[1]
- Delayline[2]*a[2]
+ Mixer_Out[0]*b[0]
+ Mixer_Out[1]*b[1]
+ Mixer_Out[2]*b[2];
offset = real(Delayline[2]*Delayline[0]);
offset_Delayline[0] = offset_Delayline[1];
offset_Delayline[1] = offset;
phase_corr = Kp*offset_Delayline[0]
+ Ki*offset_Delayline[1]
+ phase_corr
- Kp*offset_Delayline[1];
Phase = Phase + phase_corr;
Exercise 4.2
Convert the C code shown below to its equivalent fixed-point listing in C. Consider acc to be in
Q8.32 format and all the other variables to be Q1.15. Check corner cases and saturate the result if
overflow occurs. Draw a DFG of the design and map the DFG as FDA. Write RTLVerilog code of
the design. Simulate the design for a stream of input values in Q1.15 format.