Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 172

1

1

2 1

1 1 2

A B,7 C,8 D,x E,9

1 1 1 1

1

1

1

(a)

clk G clk g

E

A B C D

clk g clk g

clk G clk g clk g clk g clk G

clk G clk g

(b)

Figure 4.40 (a) Hypothetical DFG with different types of node. (b) Hardware realization

Figure 4.40(a) shows a DFG with nodes A, B, C, D and E. Node A is a combinational logic and
nodes B, C and E take 7, 8 and 9 predefined number of circuit clock cycles, respectively. Node D
dynamically executes and takes a variable number of cycles. Each black dot shows an algorithmic
delay where data from previous iteration is used in subsequent nodes. This dot in actual HW is
realized as a register that is clocked by the sampling clock. Now, having the graph and the
information about each node, a centralized controller can be easily designed or automatically
generated. Such a controller is shown in Figure 4.40(b). Each nodewith predefined number of cycles
needs a start signal from the controller, and then the controller counts the number of cycles for the
node to complete its execution. The controller then asserts an output enable signal to the register at
the output of each such node. In the figure, the output from each node is latched in a register after
assertion of an enable signal, whereas the register is clocked by the circuit clock. In the case of the
dynamic node D, the controller not only notifies the node to start its execution; the node also after
completing its execution asserts a done signal.
For the design in question, a done_D is asserted and the controller then asserts en_out_D to
latch the output from node D in a register. The input and output to the DFG and the dots on the edges
are replaced by registers clocked by sample clock clk G , whereas the rest of the logic in the nodes and
the registers at the output of each node are clocked by a circuit clock clk g . All the feedback register