Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 163

critical path. In designs where f c > f s , the iteration period ismeasured in terms of the number of clock

cycles required to compute one output sample. This definition can be trivially extended for multi-rate
systems.

4.6.2 Sampling Period and Throughput

The sampling period T s is defined as the average time between two successive data samples. The
period specifies the number of samples per second of any signal. The sampling rate or frequency
(f s ¼ 1/T s ) requirement is specific to an application and subsequently constrains the designer to
produce hardware that can process the data that is input to the systemat this rate. Often this constraint
requires the designer to minimize critical path delays. They can be reduced by usingmore optimized
computational units or by adding pipelining delays in the logic (see later). The pipelining delays
add latency in the design. In designs where f s < f c , the digital designer explores avenues of resource

sharing for optimal reuse of computational blocks.

4.6.3 Latency
Latency is defined as the time delay for the algorithm to produce an output y[n] in response to an input
x[n]. In many applications the data is processed in batches. First the data is acquired in a buffer
and then it is input for processing. This acquisition of data adds further latency in producing
corresponding outputs for a given set of inputs.
Beside algorithmic delays, pipelining registers (see later) are the main source of latency in an
FDA. In DSP applications, minimization of the critical path is usually considered to be more
important than reducing latency. There is usually an inverse relationship between critical path
and latency. In order to reduce the critical path, pipelining registers are added that result in an
increase in latency of the design. Reducing a critical path helps inmeeting the sampling requirement
of a design.
Figure 4.31 shows the sampling period as the time difference between the arrivals of two
successive samples, and latency as the time for the HW to produce a result y[n] in response to
input x[n].

input signal

y[n]

x[n]

output signal

Fully Dedicated Architecture

1T

…….
t

5T

time

time

….

0 0 1T 2T

2T 2T t

3T

3T

sample period T

latency

Figure 4.31 Latency and sampling period