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applying a large inverse voltage in the case of EEPROMs and FLASH mem-
ory cells. Whereas EEPROM were designed to be programmed and erased as
a whole, FLASH extended the technology to allow finer-grained block-level
reprogramming of storage cells.
Most digital FLASH storage devices use single-level cell (SLC), which store
a binary 1 or 0 in each cell of the chip. Another FLASH technology referred to
as multi-level cell (MLC) can store multiple values per cell as different voltage
levels. This can greatly increase storage density but is more susceptible to
failure than the SLC device.
Initially, FLASH technology was very low density and high cost, which rele-
gated it to niche applications that were extremely power constrained. However,
with improvements to the technology and silicon chip lithography, FLASH
prices have made it increasingly popular for storage in consumer electron-
ics devices such as MP3 players and digital cameras. The enormous volumes
supported by these applications has brought FLASH memory prices down to
the point that they are price competitive with high-end disk solutions and
may drop further still. Already, storage devices in laptops and other portable
computers are poised to be replaced by FLASH as an alternative.
From the standpoint of scientific applications, FLASH memory can be read
in random access fashion with little performance impact. The typical read
access latencies are less than 0.1 ms, which makes them considerably higher
performance than mechanical disk units, which offer latencies on the order
of 7 ms. However, writing data to FLASH takes considerably longer than
the read operation due to the much longer latencies required to program the
cells. Whereas read rates can be achieved that approach 200 MB/s, the write
performance is typically more on the order of tens of megabytes per second
or less. Prior to 2008, state-of-the-art NAND-FLASH-based storage devices
were typically limited to one megabyte/second peak write performance. New
high-performance double data rate (DDR) interfaces, and improvements in
the cell organization to reduce effective cell size, are enabling FLASH to push
performance past 100 MB/s write and 200 MB/s read.
One of the main problems with FLASH memory is that the cells wear out af-
ter a limited number of writes. For a typical NAND-FLASH, 98% of the blocks
can be reprogrammed at least 100,000 cycles before they fail. As FLASH
densities increase through improvements in chip lithography, the problem of
preventing cell wear-out becomes more challenging. Solid state disks attempt
to mitigate the cell wear-out problem by using load leveling algorithms. The
load-levelers attempt to spread the write operations evenly across the device
so as to reduce the chance of cell wear-out. As a result, given the practical
bandwidths available for accessing, the device would require five years of con-
tinuous access before the device will encounter cell wear-out—which is on par
with the mean time between failures (MTBF) of mechanical disk storage de-
vices. However, occasionally the load-leveling algorithm encounters degenerate
cases that result in unexpected access delays as data blocks are remapped to
maintain even distribution of the writes. The cell wear-out issues with FLASH
