Database Reference
In-Depth Information
are already available, but have had a limited impact due to market eco-
nomics or a narrow band of applications where the technology offers superior
price/performance. Others are still in development; it remains to be seen if an
effective volume-manufacturing process can be found to bring them to market.
1.7.1 Massive Array of Idle Disks (MAID)
Given current technology trends for rotating disk storage, data centers are
increasingly reliant on larger numbers of disk spindles to maintain I/O band-
width growth rates that match performance improvements of the computing
infrastructure. However, as commensurate power consumption of such system
grows, there is increasing concern for reining in the power consumed by the
storage subsystem. The concept of a massive array of idle disks (MAID) is to
power down disks that are not in use so that power savings may be realized.
A secondary benefit of powering down the disks is that they have higher re-
liability for lack of use. MAID technologies normally use SATA disks, which
allow the overall system to present an extremely dense array of disks in a
small footprint for a very competitive price.
There are several MAID technologies on the market today, and new prod-
ucts that are not explicitly MAID systems continue to adopt similar power
management features. MAID systems are typically close to the cost of enter-
prise tape drives with the reduced benefit of not being removable or scalable
as tape technology provides. There is also concern over the increased wear
and tear of the disks due to powering them on and off. In many of the mass
storage systems in production, the disk cache normally has high utilization,
and taking advantage of the power down feature would not be possible.
MAID systems are novel and timely now that power management is be-
coming a larger and larger part of storage and compute centers' planning and
design.
1.7.2 FLASH
FLASH memory is the evolution of electronically erasable programmable read-
only memory (EEPROM) technology. A FLASH memory cell, like its EEP-
ROM predecessors, is based on a field effect transistor (FET). Normally, a
FET's on/off state is controlled by charging the gate with electrons to apply
an electric field to the transistor channel. In the case of FLASH memory cells,
the FET contains a floating gate that is completely surrounded by insulating
silicon oxide. The gate is programmed by applying a high (
12V) voltage to
the electrically connected FET gate, which causes electrons to tunnel through
the insulator and into the floating gate in a process known as
hot electron
injection
or
avalanche injection.
The residual electric charge in the floating
gate provides enough energy to maintain the gate's programmed state. The
gate can be deprogrammed by exposing it to UV light in the case of ear-
lier electronically erasable programmable read-only memories (EPROM), or
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