Environmental Engineering Reference
In-Depth Information
V
DD
3
9
Receiver Circuit
R1
4
8
1
10
2
4
6
V
DD
3
7
V
DD
1
2
18
555 Timer
C2
R2
A0
VDD
5
17
6
A1
A2
A3
A4
A5
A6
A7
VSS
Decoder
VT
OSC1
OSC2
DIN
D11
D10
D9
D8
1
2
C1
3
4
5
6
16
15
14
R
OSC
V
DD
2
4
13
1
JK
Flip-Flop
6
Out
7
8
9
12
11
10
8
3
5
AND Gate
FIGURE 4.25
A schematic circuit diagram of the RF receiver circuit.
the transmitter is received. It is basically a square pulse with a width of about
0.11 s. Thus, to ensure that the JK flip-flop is triggered during the rising edge of
the clock when the signal VT sends in a pulse, the frequency of the timer is set
to 9 Hz. For the clock cycle waveform and the square pulse signal VT observed
in
Figure 4.26
, the duty cycle is set to 0.5 so that the rising edge is the same for
each cycle, and the timer components are related to the frequency,
f
= 1/0.11,
Main : 10 k
12
Clock Signal,
V
clk
10
8
6
6
4
4
2
2
VT Signal,
V
VT
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Time/sec
FIGURE 4.26
Voltage waveforms of VT and the clock cycle generated by a 555 timer.
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