Hardware Reference
In-Depth Information
Table 6.2
Summary comparison among the presented software frameworks. The classification is
based on static or dynamic power consumption, clock gating, Multiple Voltage Scaling and power
gating
Power optimization
Clock gating
MVS
Power gating
Static
Dynamic
Pure OS
CPUFreq
CPUIdle
S/R Fw
Clock Fw
V/I Fw
Cross-Layer
Centralized (
DPM
)
Distributed (
QoS
)
Hierarchical (
CPM
)
low-power design methodologies define mechanisms to solve power issues from the
physical up to the gate and architectural levels of abstraction, such methodologies
are generally based on a precise hardware support, e.g. level shifters, PLL registers
for clock signal [
10
]. In parallel, there are several software frameworks that ad-
dress power management. Hereby, we will focus on those designed for Linux-based
systems, and which were originally designed for general purpose platforms. Never-
theless, their applicability is of (quite) general validity, also for mobile embedded
systems.
The available approaches can be conveniently grouped into two categories: pure-
OS and cross-layer. The distinction comes from the power optimization mechanisms
that are applied, and which kind of interaction is exposed to higher levels. A summary
of the presented approaches is given in Table
6.2
.
The table reports the proposed classification in terms of pure-OS and cross-layer,
and for each entry a comparison is performed against the power optimization and
power optimization mechanisms involved: static versus dynamic, and clock gating
versus power gating or voltage selection. A bullet () suggests that the current entry
addresses that specific optimization, or supports that specific mechanism. Table
6.2
considers only three mechanisms for power management. Clock gating technique
aims at reducing the dynamic power consumption by disabling (i.e., gating) the input
clock signal. The frequency of the clock signal drops to zero, so that the switching
activity drops to zero, too. Multiple Voltage Scalings (MVS) refers to the use of
different power rails, providing different regions of the chip with an ad-hoc voltage
supply value. Last, power gating is the technique that cuts input voltage source, so
that reducing quadratically the consumption of dynamic power.
6.4.1
Pure-OS Techniques
Pure-OS techniques are completely implemented at the Operating System level;
they do not provide support for direct input from applications. They attempt to figure
out application requirements based on previously monitored behavior or current
activity, and enforce some control decision either on a single device or on an entire
subsystem. We can further divide these techniques in two groups, whether they tend to
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