Run-Time Resource Management at the Operating System Level - Multi-objective Design Space Exploration of Multiprocessor SoC Architectures - page 123

6.4 Power Management

Digital electronics gives enough opportunities to reduce power consumption at dif-
ferent abstraction levels, not only through silicon physical optimization [ 24 , 25 ]. As
a matter of fact, power reduction opportunity increases with higher levels of abstrac-
tions, so that from architectural up to system software layer we have enough room
to address the power/performance challenging trade-offs.
The involved abstraction levels are shown in Fig. 6.9 . We have to decouple the
SoC design in two planes: the software plane and the hardware plane. The former,
shown in Fig. 6.9 a, relates to the different levels at which the software can operate
to effectively give contribution to power consumption reduction. The latter (Fig.
6.9 b), on the other hand, refers to the design of the underlying hardware, providing
mechanisms to the upper levels of details.
From a software perspective, power reduction techniques can be employed both
statically and dynamically. Static strategies are generally addressed at compile-time
[ 7 , 22 ], or at least through ad-hoc software architecture techniques at source-code
level. Static techniques are of great importance since they can be used to exploit as
much as possible the required power/performance requirements, but these techniques
lack of flexibility. This is much more true in those systems where the workload is
not known in advance. For this scenario, dynamic approaches should be employed,
for instance at the OS level (kernel) or at higher abstraction levels [ 2 ]. Applications
can directly impact on the power/performance trade-off, but a more sophisticated
mechanism can reside at the kernel level, where the OS is aware of the entire system
status. The most complete software frameworks for the Linux kernel are reviewed
in the next sections.
From a lower level perspective, hardware has to provide the software with control
and observation points in order to ensure that the desired goal is achieved. Thus,
the power/performance trade-off solution is searched in a hardware/software co-
design approach, as it has been previously stressed in Sect. 6.2 . While conventional

Architecture

Applications

Macro−blocks

Gates and interconnections

Frameworks

Circuit

OS (kernel)

Device

Compilation

Silicon / Materials science

Source code

a b

Fig. 6.9 Power reduction and optimization techniques cover a wide range of SoC design, from both
software and hardware planes. A holistic low-power design methodology, where applicable, should
consider crossing different abstraction levels for efficient and proficient power management and
optimization. a Software design and abstraction levels, b Hardware design and abstraction levels